The present invention relates to semiconductor devices, and more particularly, to semiconductor devices having a vertical channel transistor and methods of manufacturing the same.
As the integration density of semiconductor (integrated circuit) devices increases, the size of metal-oxide-semiconductor (MOS) transistors, and thus, a channel length, of the devices generally decreases. The decrease in channel length generally enhances the integration density of semiconductor devices but may cause a short channel effect, such as drain induced barrier lowering (DIBL), hot carrier effect, and/or punch through. To prevent such a short channel effect, various techniques have been suggested, such as a decrease of the depth of a junction region and an increase of a channel length by formation of groove in a channel region.
However, as the integration density of semiconductor memory devices, in particular, dynamic random access memory (DRAM) devices, currently may be as high as a gigabit, smaller-sized MOS transistors are generally desired. In particular, MOS transistors of gigabit DRAM devices generally require a device area of 8F2 (where “F” is a minimum feature size of the device) or less. However, with currently available planar MOS transistors, in which junction regions are typically formed on both sides of a gate electrode formed on a semiconductor substrate, it is generally difficult to obtain a device area of 8 F2 or less even when a channel length of the device is scaled.